I. Field
The present disclosure generally relates to memory arrays, and more particularly, to dynamic wordline drivers and decoders for memory arrays.
II. Description of Related Art
In general, memory systems with a traditional dynamic/static circuit structure may place a heavy load on the clock. For example, in a memory structure having a plurality of wordline drivers, a single clock may drive multiple drivers and multiple address decoders, placing a large electrical load on the clock.
Additionally, each wordline driver may have its own decoded address input, which may place a large load on the decoder and which may utilize a large area of the circuit substrate, increasing complexity and power consumption. Moreover, when the clock signal is provided to multiple wordline drivers, capacitive noise coupling between the wordline driver outputs may introduce additional design complexities. Hence, there is a need for improved wordline drivers.